1. Technical Field
The present invention relates to semiconductor device and a manufacturing method thereof. Specifically, it relates to a semiconductor device including a capacitor element.
2. Related Art
When a memory region and a logic region are to be formed on one semiconductor substrate of a semiconductor device, application of a trench gate type gate electrode structure to the semiconductor device is considered to secure a channel length while making word lines (gate electrodes) smaller as disclosed in Japanese Laid-open patent publications NOs. 2002-261256, 2007-134674 and 2007-123551.
In a device disclosed in Japanese Laid-open patent publication NO. 2002-261256, a polysilicon film is used as word lines in a DRAM (Dynamic Random Access Memory) region and a logic region. Furthermore, trenches are formed only in the DRAM region, the word lines in the DRAM region are formed within the trenches and an upper surface of the DRAM region is retreated inward of an upper surface of a substrate.
Japanese Laid-open patent publication NO. 2007-134674 discloses a method of forming N type trench gate transistors in a memory cell region included in a memory region and of forming N type and P type planer transistors in N type and P type peripheral circuit regions, respectively. Specifically, an undoped silicon film is formed as a conductive protection film on a gate insulating film in the N type and P type peripheral circuit regions and a silicon nitride film is formed on this protection film. Using the silicon nitride film as a mask, gate trenches are formed in the memory cell region and a phosphorus-doped amorphous silicon film is formed on an entire surface including within the trenches. Using the silicon nitride film as a mask, a chemical mechanical polishing (CMP) and etch-back are carried out, thus burying the phosphorus-doped amorphous silicon film into the gate trenches. Thereafter, an undoped amorphous silicon film is formed on the entire surface, boron ions are selectively implanted into the P type peripheral circuit region and phosphorus ions are selectively implanted into the memory region and the N type peripheral circuit region.
As can be seen, according to the above-stated method, the protection film is provided on the gate insulating film under the silicon nitride film that serves as a mask layer for forming the gate trenches in the P type and N type peripheral circuit regions. After forming the gate trenches, the impurity-doped amorphous silicon film is formed into the gate trenches without removing the mask layer and the mask layer for forming the gate trenches is then removed. According to Japanese Laid-open patent publication NO. 2007-134674, the mask layer is removed after the doped amorphous silicon film is formed to be buried into the gate trenches. It is, therefore, possible for the protection film formed in advance to prevent damage to the gate insulating film. It is also possible to appropriately set an internal impurity concentration of a silicon layer of each gate electrode without damaging the gate insulating film in the peripheral circuit region.
Japanese Laid-open patent publication NO. 2007-123551 discloses the following technique about gate insulating films for transistors formed in a memory region and a peripheral circuit region. Since transistors to be formed in the peripheral circuit region operate at low voltage, it is necessary to make the gate oxide film thin in the peripheral circuit region. On the other hand, since boosted voltage is applied to transistors to be formed in the memory region, it is necessary to ensure high withstand voltage, that is, it is necessary to make a gate insulating film thick in the memory region.
To meet the necessity, Japanese Laid-open patent publication NO. 2007-123551 discloses a method of forming a thin oxide film that serves as a gate insulating film of planar transistors on a semiconductor substrate in the peripheral circuit region, forming gate trenches in the memory region while covering the thin oxide film with an amorphous silicon film and forming a thicker gate insulating film than the gate insulating film in the peripheral circuit region on inner walls of the gate trenches. With the method disclosed in Japanese Laid-open patent publication NO. 2007-123551, since the amorphous silicon film functions as a protection film preventing growth of the gate insulating film, it is possible to provide the thick gate insulating film while providing the thin gate insulating film in the peripheral circuit region.
Moreover, although different in technical field, Japanese Laid-open patent publication NO. 2005-285980 discloses a technique related to a transistor having a recess structure. Specifically, Japanese Laid-open patent publication NO. 2005-285980 discloses a MOS (Metal Oxide Semiconductor) field effect transistor (FET) (MOSFET) having an elevated source-drain structure. In this MOSFET, gate electrodes made of such metal as tungsten are buried in a semiconductor substrate, thus providing the recess structure.
However, according to studies of the inventor of the present invention, the conventional semiconductor device having the memory region and the logic region formed on the semiconductor substrate has the following problems to be solved so as to stably form transistors excellent as transistors in each of the memory and logic regions.
Namely, according to Japanese Laid-open patent publications NOs. 2002-261256, 2007-134674 and 2007-123551, gate electrodes for the transistors in each region are formed out of polysilicon. Due to this, as already stated above with reference to Japanese Laid-open patent publication NO. 2007-134674, it is necessary to form N+ polysilicon and P+ polysilicon by ion implantation into polysilicon after gate etching so as to form gate electrodes of conduction types in the N type and P type peripheral circuit regions, respectively. Furthermore, if trenches are formed in the memory region, polysilicon in upper portions of the trenches are substantially made thick. Since no ion implantation method is known for simultaneously forming polysilicon in the memory region as well as the other portions (such as a diffusion layer and gates in the logic region). Due to this, procedures of the method are such that after polysilicon outside of the trenches is removed, polysilicon is formed again. This makes manufacturing steps complicated and it leaves much room for improvement in stability of manufacturing of transistors. Specifically, because of irregularities in finished trench depth, ion implantation dose is irregular in depth direction. As a result, such problems as impurities penetration in the gate insulating film and depletion of the gate electrodes disadvantageously occur. Moreover, because of separate ion implantation for P+ polysilicon and N+ polysilicon, the number of steps increases, manufacturing stability is poor, and sufficiently high process reproducibility and mass productivity cannot be ensured. These problems are more conspicuous as scale-down and high integration progress.